1. Field of the Invention
The present invention relates to a CMOS image sensor in which fixed pattern noise in a CMOS image sensor aimed at improving the performance of an imaging semiconductor device can be reduced and a method of manufacturing the same.
2. Description of the Prior Art
FIGS. 23A-23C each are a sectional view showing a conventional CMOS image sensor and the manufacturing method thereof. The figures show a semiconductor substrate 100 such as Si substrate, a gate electrode 1, a gate insulating film 2, a doped polysilicon layer 3, a WSi2 layer 4, a sidewall-forming film (TEOS oxide film) 5, a LOCOS isolation film 6, an etching-damaged layer 10, a photodiode region 15, a sidewall 19, an N well area 30 in the Si substrate, and a peripheral circuit 31.
In a recent system LSI (logic LSI), the on-chip integration in one LSI of a functional module for system-on-chip has become very important, and it can be said that the block of a CMOS image sensor is one of the modules. In order to enable the system-on-chip, it is important to develop the module of the CMOS image sensor based on a conventional logic process.
The method of manufacturing the conventional CMOS image sensor will next be described by referring to FIGS. 23A-23C.
First of all, the LOCOS isolation film 6 is formed on the surface of the semiconductor substrate 100 containing the peripheral circuit 31 and the photodiode region 15, and then the gate electrode 1 is formed on the surface corresponding to the peripheral circuit 31 within the surface of the semiconductor substrate 100 (FIG. 23A).
The gate electrode 1 consists of the three-layered structure formed in the order of the gate insulating film 2, doped polysilicon layer 3, and WSi2 layer 4 on the surface of the semiconductor substrate 100 (herein, on the surface of the N well region 30 formed in the semiconductor substrate 100).
After the state as shown in FIG. 23A, if required, an N-/P-ion implantation for the formation of LDD (Lightly Doped Drain) structure is occasionally done. However, since such an implantation is no direct relationship to a description herein, it will be omitted.
Then, the sidewall-forming film 5 is deposited in a thickness in the order of 1,000-3,000 angstroms all over the surface of the semiconductor substrate 100 (FIG. 23B). As the film to be deposited, a TEOS oxide film is adopted herein. The film thickness thereof is different depending on the generation of the design rule. However, the typical thickness is in the order of 1,000-3,000 angstroms in many cases.
Subsequently, the whole surface of the semiconductor substrate 100 is subjected to etch-back process (referred to as “blanket E/B” hereinafter) without using a mask (FIG. 23C).
Referring to FIG. 23C, a film is formed also in the direction orthogonal to the sidewall on the sidewall portion of a structure rising perpendicularly like a portion of the three-layered structure of the gate electrode 1. Accordingly, the film thickness in the vertical direction of the film formed on the sidewall portion is larger than the thickness in the vertical direction of the film formed on top of the three-layered structure (the upper surface of the WSi2 layer 4). Therefore, if the amount of over-etching by blanket E/B is properly selected, the film existing in the portion other than the sidewall portion of the three-layer structure is removed, to thereby form the sidewall 19 on the sidewall portion of the three-layered structure as shown in FIG. 23C.
Herein, since there exist variations in the film thickness of the sidewall-forming film 5, the “over etching” is typically performed for a period of time corresponding to 10-40% of “just etching” time in order to eliminate the sidewall-forming film 5 which may be remained as etching residues in all the portions other than the sidewall portion. This over-etching causes plasma damage on the surface of the semiconductor substrate 100 in which a transistor is to be formed except a portion on which the LOCOS isolation film 6 is formed. This plasma damage forms the etching-damaged layer 10 on the surface of the semiconductor substrate 100 containing the surface of the N well area 30. A level which may trap carriers is formed in the etching-damaged layer 10. Moreover, since the LOCOS isolation film 6 is exposed to the plasma for over-etching, the field edge (bird's beak) of the LOCOS isolation film 6 that is the outer edge portion thereof is particularly greatly influenced by the damage caused by the plasma.
Since the conventional CMOS image sensor and the manufacturing method thereof are constructed as mentioned above, there have been the following drawbacks therein. That is, when the etching-damaged layer 10 is formed in the photodiode region, the conversion efficiency of photoelectric conversion by the photodiode reduces; the junction leakage is caused at the field edge (bird's beak) of the LOCOS isolation film 6 that is greatly influenced by the damage caused by the plasma; and FPN (Fixed Pattern Noise) becomes high, to thereby degrade the performance of the sensor.